Synopsys Solutions

The flow begins with defining the high-level architecture and design specifications for the chip. Synopsys provides tools for creating functional and performance models, as well as architectural exploration tools to optimize the design for power, performance, and area.

• 3DIC Compiler: The Synopsys 3DIC Compiler platform is a complete, end-to-end solution for efficient, 2.5D, and 3D multi-die system integration.
• Platform Architect: Provides architects and system designers with SystemC™ TLM-based tools and efficient methods for early analysis and optimization of multicore SoC architectures for performance and power.

Register Transfer Level (RTL) design involves creating the digital logic description of the chip. Synopsys tools aid in RTL coding, verification, and synthesis, converting the design into gates and optimizing it for power, performance, and area.

• Design Compiler: Handles RTL coding, synthesis, and optimization for power, performance, and area.
• Fusion Compiler: Fusion Compiler features a unique RTL-to-GDSII architecture that enables customers to reimagine what is possible from their designs and take the fast path to achieving maximum differentiation.
• Custom Compiler: As the heart of the Synopsys Custom Design Family, Custom Compiler provides design entry, simulation management and analysis, and custom layout editing features.

Ensuring the correctness of the design is paramount. Synopsys' verification tools encompass simulation, emulation, and formal verification techniques. They help identify and resolve functional errors and ensure the design behaves as expected.

• VCS (Verilog Compiler Simulator): A high-performance simulation tool for verifying the correctness of the design.
• VC SpyGlass: Synopsys VC SpyGlass integrates advanced algorithms and analysis techniques that provides designers detailed information and insights about their design much earlier in the RTL phase.
• Verdi: Enables comprehensive debug for all design and verification flows. It includes powerful technology that helps you comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.
• VSO.ai: Synopsys VSO.ai™ (Verification Space Optimization) delivers the industry’s first AI-driven verification solution to help verification teams achieve coverage closure faster and with higher quality.
• PrimeSim: PrimeSim™ SPICE is a high-performance SPICE circuit simulator for analog, RF, and mixed-signal applications.

This stage involves translating the logical design into a physical layout. Synopsys tools assist in floorplanning, placement, routing, and chip assembly, optimizing for manufacturability and performance.

• Fusion Compiler: Fusion Compiler features a unique RTL-to-GDSII architecture that enables customers to reimagine what is possible from their designs and take the fast path to achieving maximum differentiation.
• DSO.ai: DSO.ai searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area.
• Custom Compiler: As the heart of the Synopsys Custom Design Family, Custom Compiler provides design entry, simulation management and analysis, and custom layout editing features.

• Custom Compiler: Tool for custom layout design of analog and mixed-signal circuits.
• PrimeSim HSPICE: PrimeSim HSPICE is the industry’s ‘gold standard’ for accurate circuit simulation and offers foundries-certified MOS device models with state-of-the-art simulation and analysis algorithms.

Synopsys' design analysis and signoff solution includes a broad portfolio of products for static timing analysis, advanced signal integrity, power and power integrity, parasitic extraction, ECO closure, transistor-level analysis and library characterization.

• PrimeTime: Enables power analysis and optimization.
• PrimePower: Power analysis tool for estimating power consumption and optimizing power distribution networks.
• StarRC: The StarRC™ solution is the EDA industry’s gold standard for parasitic extraction.
• IC Validator: Synopsys IC Validator™ physical verification high-performance signoff solution improves productivity for customers at all process nodes, from mature to advanced.

Synopsys integrated Silicon Lifecycle Management (SLM) family of products improves silicon health and operational metrics at every phase of the device lifecycle. Synopsys SLM family of products is built on a foundation of enriched in-chip observability, analytics and integrated automation. Monitors enable deep insights from silicon to system. Meaningful data is gathered at every opportunity for continuous analysis and actionable feedback.

• TestMAX: The Synopsys TestMAX™ family of products offers innovative, next-level test and diagnosis capabilities for all digital, memory and analog portions of a semiconductor device.
• DFT/ATPG: ATPG is Synopsys’ state-of-the-art pattern generation solution that enables design teams to meet their test quality and cost goals with unprecedented speed.
• TSO.ai: TSO.ai automatically searches for an optimal solution in a large test search space to minimize pattern count and ATPG turn-around time reducing test costs dramatically.
• PVT Sensors: As the name implies, PVT sensors represent embedded analog IP blocks that are typically integrated into SoCs with the goal of sensing the process variability and operating environment of the chip. These devices exploit the fact that certain measurable characteristics of a semiconductor device change depending on levels of activity, due to variable software operation or CPU loading, and also from environmental conditions.
• Path-Margin IP: Path selection logic, RTL configuration and generation, connecting to functional and/or test paths, synthesis, implementation, timing validation and path qualification are the key functions addressed by the EDA automation provided.

Synopsys tools enable the creation of FPGA-based prototypes and hardware emulators for early software development and system validation.

• HAPS Prototyping Solution: Enables FPGA-based prototypes for software development and system validation.
• Zebu Server: Provides hardware emulation capabilities.

The smart manufacturing solutions from Synopsys are built upon Synopsys’ extensive expertise in IC design, mask synthesis, process modeling, on-chip test and monitoring techniques and cloud-based data analytics.

• Proteus OPC: achieve exceptional precision, efficiency and speed in proximity correction, model building for correction, and analyzing proximity effects on corrected and uncorrected IC layout patterns, revolutionizing your chip fabrication process.
• Sentaurus: Sentaurus Process is an advanced 1D, 2D and 3D process simulator for developing and optimizing silicon semiconductor process technologies.
• TCAD: Synopsys TCAD offers a comprehensive suite of products that includes industry-leading process and device simulation tools, as well as a powerful graphical user interface (GUI) driven simulation environment for managing simulation tasks and analyzing simulation results.
• BISTel Yield Management: BISTel solutions collect, manage, and analyze data, monitor the health of equipment, optimize process flows, identify the root cause of failures rapidly, and predict outcomes to mitigate manufacturing risks.